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USB2231/USB2232
5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
PRODUCT FEATURES
CIR Controller Consumer IR (CIR) Controller with support for all popular CIR formats. Flash Media Controller Complete System Solution for interfacing SmartMediaTM (SM) or xD Picture CardTM (xD)1, Memory StickTM (MS), High Speed Memory Stick (HSMS), Memory Stick PRO (MSPRO), MS DuoTM, Secure Digital (SD), High Speed SD, Mini-Secure Digital (Mini-SD), TransFlash (SD), MultiMediaCardTM (MMC), Reduced Size MultiMediaCard (RS-MMC), NAND Flash, Compact FlashTM (CF) and CF UltraTM I & II, and CF formfactor ATA hard drives to Hi-Speed USB
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Datasheet
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12K Bytes of internal SRAM for general purpose scratchpad 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM Two, Double Buffered Bulk Endpoints Two, Bi-directional 512 Byte Buffers for Bulk Endpoints 64 Byte RX Control Endpoint Buffer 64 Byte TX Control Endpoint Buffer 76K Byte Internal Code Space or Optional 128K Byte External Code Space using Flash, SRAM or EPROM memory.
Internal or External Program Memory Interface
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Supports USB Bulk Only Mass Storage Compliant Bootable BIOS

Support for simultaneous operation of all above devices. (only one at a time of each of the following groups supported: CF or ATA drive, SM or XD or NAND, SD or MMC) On-Chip 4-Bit High Speed Memory Stick and MS PRO Hardware Circuitry On-Chip firmware reads and writes High Speed Memory Stick and MS PRO 1-bit ECC correction performed in hardware for maximum efficiency Hardware support for SD Security Command Extensions On-chip power FETs with short circuit protection for supplying flash media card power USB Bus Power Certified 3.3 Volt I/O with 5V input tolerance on VBUS/GPIO3 Complete USB Specification 2.0 Compatibility for Bus Powered Operation
-- -- Includes Hi-Speed USB Transceiver A Bi-directional Control and two Bi-directional Bulk Endpoints are provided. Provides low speed control functions 30 Mhz execution speed at 1 clock per instruction cycle average
On Board 24Mhz Crystal Driver Circuit Can be clocked by 48MHz external source On-Chip 1.8V Regulator for Low Power Core Operation Internal PLL for 480Mhz Hi-Speed USB Sampling, Configurable MCU clock Supports firmware upgrade via USB bus if "boot block" Flash program memory is used 12 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.
-- Inputs capable of generating interrupts with either edge sensitivity Activity LED polarity/operation/blink rate Full or Partial Card compliance checking Bus or Self Powered LUN configuration and assignment Write Protect Polarity SmartDetachTM - Detach from USB when no Card Inserted for Notebook apps Cover Switch operation for xD compliance Inquiry Command operation SD Write Protect operation Older CF card support Force USB 1.1 reporting Internal or External Power FET operation
Attribute bit controlled features:
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8051 8 bit microprocessor
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Compatible with Microsoft WinXP, WinME, Win2K SP3, Apple OS10, Softconnex, and Linux Multi-LUN Mass Storage Class Drivers Win2K, Win98/98SE and Apple OS8.6 and OS9 Multi-LUN Mass Storage Class Drivers available from SMSC 128 Pin TQFP Package (1.0mm height, 14mmx14mm footprint); green, lead-free package also available.
1.xD Picture Card not applicable to USB2231
SMSC USB2231/USB2232
DATASHEET
Revision 1.3 (07-12-05)
5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
ORDER NUMBER(S):
USB2231/USB2232-NE-03 FOR 128 PIN, TQFP PACKAGE; USB2231/USB2232-NU-03 FOR 128 PIN, TQFP PACKAGE (GREEN LEAD-FREE) PACKAGE
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) 2005 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 3 Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 3.2 128-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 128-Pin List Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1 6.2 PIN Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 7 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 7.2 7.3 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 9 GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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List of Figures
Figure 5.1 USB2231/USB2232 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 8.1 USB2231/USB2232 128-Pin TQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of Tables
Table 3.1 Table 3.2 Table 6.1 Table 6.2 Table 8.1 Table 9.1 USB2231/USB2232 128-Pin Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USB2231/USB2232 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 USB2231/USB2232 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 USB2231/USB2232 Buffer Type Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 USB2231/USB2232 128-Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Chapter 1 General Description
The USB2231/USB2232 is a Hi-Speed USB Consumer IR and Bulk Only Mass Storage Class Peripheral Controller. The Bulk Only Mass Storage Class Peripheral Controller supports CompactFlash (CF) in True IDE Mode only, SmartMedia (SM), Memory Stick (MS) including both serial and parallel interface and Secure Digital/MultiMediaCard (SD/MMC) flash memory devices. It provides a single chip solution for the most popular flash memory cards in the market. In addition, the CIR controller consists of the SMSC CIrCC block, which includes a Synchronous Communications Engine (SCE) and hardware demodulators for the supported CIR formats. The device consists of a USB2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad, and program SRAM, and CIR, CF, MS, SM and SD controllers. The SD controller supports both SD and MMC devices. Provisions for external Flash Memory up to 128K bytes for program storage is provided (note: when Bank switching is enabled the upper 64K will map into the 8051 ROM space, otherwise, only the first 64K bytes is used). 12K bytes of scratchpad SRAM and 768Bytes of program SRAM are also provided. Twelve GPIO pins are provided for indicators, external serial EEPROM for OEM ID and system configuration information, and other special functions. Internal power FETs are provided to directly supply power to the xD/SM, MMC/SD and MS/MSPro cards. The internal ROM program is capable of implementing any combination of single or multi-LUN CF/SD/MMC/SM/MS reader functions with individual card power control and activity indication. SMSC also provides licenses** for Win98 and Win2K drivers and setup utilities. Note: Please check with SMSC for precise features and capabilities for the current ROM code release.
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other intellectual property rights from or through various persons or entities, including without limitation media standard companies, forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses or technical information available; does not promise or represent that any such licenses or technical information will actually be obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State Disk Patents. SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE. No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC.
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Chapter 2 Acronyms
SM: SmartMedia SMC: SmartMedia Controller FM: Flash Media FMC: Flash Media Controller CF: Compact Flash CFC: CompactFlash Controller SD: Secure Digital SDC: Secure Digital Controller MMC: MultiMediaCard MS: Memory Stick MSC: Memory Stick Controller TPC: Transport Protocol Code. ECC: Error Checking and Correcting CRC: Cyclic Redundancy Checking
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Chapter 3 Pin Table
3.1 128-Pin Package
Table 3.1 USB2231/USB2232 128-Pin Package
CompactFlashINTERFACE (28 Pins) CF_D0 CF_D4 CF_D8 CF_D12 CF_nIOR CF_IORDY CF_SA1 CF_D1 CF_D5 CF_D9 CF_D13 CF_nIOW CF_nCS0 CF_SA2 CF_D2 CF_D6 CF_D10 CF_D14 CF_IRQ CF_nCS1 CF_nCD1 CF_D3 CF_D7 CF_D11 CF_D15 CF_nRESET CF_SA0 CF_nCD2
SmartMedia INTERFACE (17 Pins) SM_D0 SM_D4 SM_ALE SM_nWP SM_nWPS Memory Stick INTERFACE (7 Pins) MS_BS MS_D1 MS_SDIO/MS_D0 MS_D2 SD INTERFACE (7 Pins) SD_CMD SD_DAT2 SD_CLK SD_DAT3 SD_DAT0 SD_nWP SD_DAT1 MS_SCLK MS_D3 MS_INS SM_D1 SM_D5 SM_CLE SM_nB/R SM_D2 SM_D6 SM_nRE SM_nCE SM_D3 SM_D7 SM_nWE SM_nCD
USB INTERFACE (10 Pins) USBDP VDD18PLL XTAL1/CLKIN USBDM VSSPLL XTAL2 ATEST VDDA33 RBIAS VSSA
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Table 3.1 USB2231/USB2232 128-Pin Package (continued)
MEMORY/IO INTERFACE (27 Pins) MA0/CLK_SEL0 MA4 MA8 MA12 MD0 MD4 nMRD MA1/CLK_SEL1 MA5 MA9 MA13 MD1 MD5 nMWR MISC (15 Pins) GPIO1 GPIO5 GPIO9 nTEST0 GPIO2 GPIO6/ROMEN/MA16 GPIO10/ CRD_PWR1 nTEST1 CIR (1 PIN) IR_RXD DIGITAL, POWER, GROUND & NC (16 Pins) (5)VDD33 (2)VDD18 Total 128 (7)VSS (2)NC GPIO3 GPIO7 GPIO11/ CRD_PWR2 nRESET GPIO4 GPIO8/ CRD_PWR0 GPIO12 MA2/SEL_CLKDRV MA6 MA10 MA14 MD2 MD6 nMCE MA3/TX_POL MA7 MA11 MA15 MD3 MD7
3.2
128-Pin List Table
Table 3.2 USB2231/USB2232 128-Pin TQFP
PIN # 1 2 3 4 5 6 7 8
NAME MA13 MA14 VDD33 MA15 MD0 MD1 MD2 MD3
MA 8 8 8 8 8 8 8
PIN # 33 34 35 36 37 38 39 40
NAME CF_D1 CF_D2 CF_D3 CF_D4 CF_D5 CF_D6 CF_D7 CF_D8
MA 8 8 8 8 8 8 8 8
PIN # 65 66 67 68 69 70 71 72
NAME SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7
MA 8 8 8 8 8 8 8 8
PIN # 97 98 99 100 101 102 103 104
NAME VSS RBIAS ATEST VDD33 VDD18PLL XTAL1/ CLKIN XTAL2 VSSPLL
MA -
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Table 3.2 USB2231/USB2232 128-Pin TQFP (continued) PIN # 9 10 11 12 13 NAME MD4 MD5 MD6 MD7 nMRD MA 8 8 8 8 8 PIN # 41 42 43 44 45 NAME CF_D9 GPIO8/ CRD_PWR0 VDD33 GPIO11/ CRD_PWR2 CF_D10 MA 8 8 8 8 PIN # 73 74 75 76 77 NAME SM_ALE SM_nWP SM_CLE SM_nWPS SM_nB/R MA 8 8 8 PIN # 105 106 107 108 109 NAME GPIO9 VDD18 GPIO7 VDD33 GPIO6/ ROMEN/ MA16 GPIO5 GPIO4 VSS nRESET GPIO2 GPIO1 MA0/ CLK_SEL0 MA1/ CLK_SEL1 MA2/ SEL_ CLKDRV MA3/ TX_POL MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA 8 8 8
14 15 16 17 18 19 20 21 22
nMWR VSS VSS nMCE MS_INS MS_D0/ MS_SDIO MS_D1 MS_D2 MS_D3
8 8 8 8 8 8
46 47 48 49 50 51 52 53 54
CF_D11 VSS CF_D12 VDD18 CF_D13 CF_D14 CF_D15 CF_nCD1 CF_nCD2
8 8 8 8 8 -
78 79 80 81 82 83 84 85 86
SM_nCD GPIO10/ CRD_PWR1 VDD33 SM_nRE SM_nWE SM_nCE VSS VSS VSSA
8 8 8 8 -
110 111 112 113 114 115 116 117 118
8 8 8 8 8 8 8
23 24 25 26 27 28 29 30 31 32
MS_ SCLK MS_BS SD_nWP SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_CMD SD_CLK CF_D0
8 8 8 8 8 8 8 8
55 56 57 58 59 60 61 62 63 64
CF_IRQ CF_IORDY CF_nIOR CF_nIOW CF_nRESET CF_nCS0 CF_nCS1 CF_SA0 CF_SA1 CF_SA2
8 8 8 8 8 8 8 8 8 -
87 88 89 90 91 92 93 94 95 96
USBDM USBDP VDDA33 NC IR_RXD NC GPIO12 GPIO3 nTEST1 nTEST0
8 8 8 8 8 -
119 120 121 122 123 124 125 126 127 128
8 8 8 8 8 8 8 8 8 8
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Chapter 4 Block Diagram
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Chapter 5 Pin Configuration
Figure 5.1 USB2231/USB2232 128-Pin TQFP
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Chapter 6 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "n" symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "n" is not present before the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signal. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.
6.1
PIN Descriptions
Table 6.1 USB2231/USB2232 Pin Descriptions
NAME SYMBOL BUFFER TYPE DESCRIPTION
CompactFlash (In True IDE mode) INTERFACE CF Chip Select 1 CF Chip Select 0 CF Register Address 2 CF Register Address 1 CF Register Address 0 CF Interrupt CF Data 15-8 CF_nCS1 CF_nCS0 CF_SA2 CF_SA1 CF_SA0 CF_IRQ CF_D[15:8] O8PU O8PU O8 O8 O8 IPD I/O8PD This pin is the active low chip select 1 signal for the CF ATA device This pin is the active low chip select 0 signal for the task file registers of CF ATA device in the True IDE mode. This pin is the register select address bit 2 for the CF ATA device. This pin is the register select address bit 1 for the CF ATA device This pin is the register select address bit 0 for the CF ATA device. This is the active high interrupt request signal from the CF device. The bi-directional data signals CF_D15-CF_D8 in True IDE mode data transfer. In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pulldown resistor. CF Data7-0 CF_D[7:0] I/O8PD The bi-directional data signals CF_D7-CF_D0 in the True IDE mode data transfer. In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pulldown resistor. IO Ready CF_IORDY IPU This pin is active high input signal. This pin has an internally controlled weak pull-up resistor.
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Table 6.1 USB2231/USB2232 Pin Descriptions
NAME CF Card Detection2 SYMBOL CF_nCD2 BUFFER TYPE IPU DESCRIPTION This card detection pin is connected to the ground on the CF device, when the CF device is inserted. This pin has an internally controlled weak pull-up resistor. CF Card Detection1 CF_nCD1 IPU This card detection pin is connected to ground on the CF device, when the CF device is inserted. This pin has an internally controlled weak pull-up resistor. CF Hardware Reset CF IO Read CF IO Write Strobe CF_nRESET CF_nIOR CF_nIOW O8 O8 O8 This pin is an active low hardware reset signal to CF device. This pin is an active low read strobe signal for CF device. This pin is an active low write strobe signal for CF device.
SmartMedia INTERFACE SM Write Protect SM_nWP O8PD This pin is an active low write protect signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled SM Address Strobe SM_ALE O8PD This pin is an active high Address Latch Enable signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled SM Command Strobe SM_CLE O8PD This pin is an active high Command Latch Enable signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled SM Data7-0 SM_D[7:0] I/O8PD These pins are the bi-directional data signal SM_D7SM_D0. The bi-directional data signal has an internal weak pulldown resistor. SM Read Enable SM_nRE 08PU This pin is an active low read strobe signal for SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET. 08 If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pullups must be used, and should be connected to the applicable Card Power Supply).
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Table 6.1 USB2231/USB2232 Pin Descriptions
NAME SM Write Enable SYMBOL SM_nWE BUFFER TYPE O8PU DESCRIPTION This pin is an active low write strobe signal for SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET. 08 If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pullups must be used, and should be connected to the applicable Card Power Supply). A write-protect seal is detected, when this pin is low. This pin has an internally controlled weak pull-up resistor. SM_nB/R I This pin is connected to the BSY/RDY pin of the SM device. An external pull-up resistor is required on this signal. The pull-up resistor must be pulled up to the same power source that powers the SM/NAND flash device. SM Chip Enable SM_nCE O8PU This pin is the active low chip enable signal to the SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET. 08 If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pullups must be used, and should be connected to the applicable Card Power Supply). This is the card detection signal from SM device to indicate if the device is inserted. This pin has an internally controlled weak pull-up resistor. MEMORY STICK INTERFACE MS Bus State MS_BS O8 This pin is connected to the BS pin of the MS device. It is used to control the Bus States 0, 1, 2 and 3 (BS0, BS1, BS2 and BS3) of the MS device. MS_SDIO/MS_ D0 I/O8PD This pin is a bi-directional data signal for the MS device. Most significant bit (MSB) of each byte is transmitted first by either MSC or MS device. The bi-directional data signal has an internal weak pulldown resistor. MS System Data In/Out MS_D[3:1] I/O8PD This pin is a bi-directional data signal for the MS device. The bi-directional data signals have internal weak pulldown resistors.
SM Write Protect Switch
SM_nWPS
IPU
SM Busy or Data Ready
SM Card Detection
SM_nCD
IPU
MS System Data In/Out
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Table 6.1 USB2231/USB2232 Pin Descriptions
NAME MS Card Insertion SYMBOL MS_INS BUFFER TYPE IPU DESCRIPTION This pin is the card detection signal from the MS device to indicate, if the device is inserted. This pin has an internally controlled weak pull-up resistor. MS System CLK MS_SCLK O8 This pin is an output clock signal to the MS device. The clock frequency is software configurable. SD INTERFACE SD Data3-0 SD_DAT[3:0] I/O8PU These are bi-directional data signals. These pins have internally controlled weak pull-up resistors. SD_CLK O8 This is an output clock signal to SD/MMC device. The clock frequency is software configurable. SD Command SD_CMD I/O8PU This is a bi-directional signal that connects to the CMD signal of SD/MMC device. This pin has an internally controlled weak pull-up resistor. SD Write Protected SD_nWP IPD This pin is an input signal with an internal weak pulldown. This pin has an internally controlled weak pull-down resistor. USB INTERFACE USB Bus Data USB Transceiver Bias Analog Test USBDM USBDP RBIAS IO-U I These pins connect to the USB bus data signals. A 12.0k, 1.0% resistor is attached from VSSA to this pin, in order to set the transceiver's internal bias currents. This signal is used for testing the analog section of the chip and should be connected to VDDA33 for normal operation. 1.8v Power for the PLL Ground Reference for 1.8v PLL power 3.3v Analog Power Analog Ground Reference for 3.3v Analog Power. ICLKx 24Mhz Crystal or external 24/48 MHz clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 24/48Mhz clock when a crystal is not used. Note: The `MA[2:0] pins will be sampled while nRESET is asserted, and the value will be latched upon nRESET negation. This will determine the clock source and value.
SMSC USB2231/USB2232
SD Clock
ATEST
AIO
1.8v PLL Power PLL Ground Reference 3.3v Analog Power Analog Ground Reference Crystal Input/External Clock Input
VDD18PLL VSSPLL VDDA33 VSSA XTAL1/ CLKIN
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Table 6.1 USB2231/USB2232 Pin Descriptions
NAME Crystal Output SYMBOL XTAL2 BUFFER TYPE OCLKx DESCRIPTION 24Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit.
MEMORY/IO INTERFACE Memory Data Bus MD[7:0] IO8 When ROMEN bit of GPIO_IN1 register = 0, these signals are used to transfer data between the internal CPU and the external program memory. These pins have internally controlled weak pull-up resistors. Memory Address Bus Memory Address Bus MA[15:3] MA3/ TX_POL O8 I/O8PU These signals address memory locations within the external memory. MA3 Addresses memory locations within the external memory. During nRESET assertion, TX_POL will select the operating polarity of the IR LED (active high or active low) and the weak pull-up resistor will be enabled. When nRESET is negated, the value on this pin will be internally latched and this pin will revert to MA3 functionality, the internal pull-up will be disabled. Memory Address Bus MA2/ SEL_CLKDRV I/O8PD MA2 Addresses memory locations within the external memory. SEL_CLKDRV. During nRESET assertion, this pins will select the operating clock mode (crystal or externally driven clock source), and a weak pull-down resistor is enabled. When nRESET is negated, the value will be internally latched and this pin will revert to MA2 functionality, the internal pull-down will be disabled. `0' = Crystal operation (24MHz only) `1' = Externally driven clock source (24MHz or 48MHz) If the latched value is `1', then the MA2 pin is tri-stated when the following conditions are true: 1. IDLE bit (PCON.0) is 1. 2. INT2 is negated 3. SLEEP bit of CLOCK_SEL is 1. If the latched value is `0', then the MA2 pin will function identically to the MA[15:3] pins at all times (other than during nRESET assertion). Note:
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DATASHEET
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Table 6.1 USB2231/USB2232 Pin Descriptions
NAME Memory Address Bus SYMBOL MA[1:0]/CLK_S EL[1:0] BUFFER TYPE I/O8PD DESCRIPTION MA[1:0], These signals address memory locations within the external memory. SEL[1:0]. During nRESET assertion, these pins will select the operating frequency of the external clock, and the corresponding weak pull-down resistors are enabled. When nRESET is negated, the value on these pins will be internal latched and these pins will revert to MA[1:0] functionality, the internal pull-downs will be disabled. SEL[1:0] SEL[1:0] SEL[1:0] SEL[1:0] Note: = = = = `00'. 24MHz `01'. RESERVED `10'. RESERVED `11'. 48MHz
If the latched value is `1', then the corresponding MA pin is tri-stated when the following conditions are true: 1. IDLE bit (PCON.0) is 1. 2. INT2 is negated 3. SLEEP bit of CLOCK_SEL is 1. If the latched value is `0', then the corresponding MA pin will function identically to the MA[15:3] pins at all times (other than during nRESET assertion). Memory Write Strobe Memory Read Strobe Memory Chip Enable nMWR nMRD nMCE O8 O8 O8 Program Memory Write; active low Program Memory Read; active low Program Memory Chip Enable; active low. This signal is asserted, when any of the following conditions are no longer met: 1. IDLE bit (PCON.0) is 1. 2. INT2 is negated 3. SLEEP bit of CLOCK_SEL is 1. Note: MISC General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 I/O8 I/O8 I/O8 I/O8 I/O8 This pin may be used either as input, edge sensitive interrupt input, or output. This pin may be used either as input, edge sensitive interrupt input, or output. This pin may be used either as input, edge sensitive interrupt input, or output. This pin may be used either as input, edge sensitive interrupt input, or output. This pin may be used either as input, edge sensitive interrupt input, or output. This signal is held to a logic `high' while nRESET is asserted.
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DATASHEET
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Table 6.1 USB2231/USB2232 Pin Descriptions
NAME GPIO6, ROMEN, Memory Address 16 SYMBOL GPIO6/ROMEN /MA16 BUFFER TYPE IPU DESCRIPTION This pin has an internal weak pull-up resistor that is enabled or disabled by the state of nRESET. The pull-up is enabled when nRESET is active. The pull-up is disabled, when the nRESET is inactive (some clock cycles later, after the rising edge of nRESET). The state of this pin is latched internally on the rising edge of nRESET to determine if internal or external program memory is used. The state latched is stored in ROMEN bit of GPIO_IN1 register. I/O8 After the rising edge of nRESET, this pin may be used as GPIO6 or RXD. When pulled low via an external weak pull-down resistor, an external program memory should be connected to the memory data bus. The USB2231/USB2232 uses this external bus for program execution. When this pin is left unconnected or pulled high by a weak pull-up resistor, the USB2231/USB2232 uses the internal ROM for program execution. I/O8 For Bank Switching support, MA16 addresses the external 128k memory above the standard 64k range (the upper 64k is mapped into the 64k addressable ROM space) This pin may be used either as input, edge sensitive interrupt input, or output. GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ 100mA. GPIO9 GPIO10/ CRD_PWR1 I/O8 I/O8 This pin may be used either as input, edge sensitive interrupt input, or output. GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ 100mA. GPIO11/ CRD_PWR2 I/O8 GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ 200mA. GPIO12 nRESET nTEST[1:0] I/O8 IS I These pins may be used either as input, or output. This active low signal is used by the system to reset the chip. The active low pulse should be at least 1s wide. These signals are used for testing the chip. User should normally tie them high externally, if the test function is not used.
General Purpose I/O General Purpose I/O Or Card Power General Purpose I/O General Purpose I/O Or Card Power General Purpose I/O Or Card Power General Purpose I/O RESET input TEST Input
GPIO7 GPIO8/ CRD_PWR0
I/O8 I/O8
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DATASHEET
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Table 6.1 USB2231/USB2232 Pin Descriptions
NAME SYMBOL BUFFER TYPE CIR IR Receive Data IR_RXD I IR_RXD, is the CIR receiver input. DESCRIPTION
DIGITAL POWER, GROUNDS, and NO CONNECTS 1.8v Digital Core Power VDD18 +1.8V Core power All VDD18 pins must be connected together on the circuit board. VDD33 3.3V Power & Regulator Input. Pins 100 & 108 supply 3.3V power to the internal 1.8V regulators. VSS Ground Reference
3.3v Power & & Voltage Regulator Input Ground Notes:
Hot-insertion capable card connectors are required for all flash media. It is required for SD connector to have Write Protect switch. This allows the chip to detect MMC card. nMCE is normally asserted except when the 8051 is in standby mode.
6.2
Buffer Type Descriptions
Table 6.2 USB2231/USB2232 Buffer Type Descriptions
BUFFER I IPU IPD IS I/O8 I/O8PU I/O8PD O8 O8PU O8PD ICLKx OCLKx I/O-U AIO Input Input with internal weak pull-up resistor. Input with internal weak pull-down resistor. Input with Schmitt trigger Input/Output buffer with 8mA sink and 8mA source. Input/Output buffer with 8mA sink and 8mA source, with an internal weak pull-up resistor. Input/Output buffer with 8mA sink and 8mA source, with an internal weak pull-down resistor. Output buffer with 8mA sink and 8mA source. Output buffer with 8mA sink and 8mA source, with an internal weak pull-up resistor. Output buffer with 8mA sink and 8mA source, with an internal weak pull-down resistor. XTAL clock input XTAL clock output Analog Input/Output Defined in USB specification Analog Input/Output
20 SMSC USB2231/USB2232
DESCRIPTION
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DATASHEET
5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Chapter 7 DC Parameters
7.1 Maximum Guaranteed Ratings
Operating Temperature Range ............................................................................................0oC to +70oC Storage Temperature Range............................................................................................. -55o to +150oC Lead Temperature Range (soldering, 10 seconds) ...................................................................... +325oC Positive Voltage on GPIO3, with respect to Ground......................................................................... 5.5V Positive Voltage on any signal pin, with respect to Ground ............................................................. 4.6V Positive Voltage on XTAL1, with respect to Ground ......................................................................... 4.0V Positive Voltage on XTAL2, with respect to Ground ......................................................................... 2.5V Negative Voltage on GPIO8, 10 & 11, with respect to Ground (see Note 7.2)............................... -0.5V Negative Voltage on any pin, with respect to Ground ..................................................................... -0.5V Maximum VDD18, VDD18PLL .............................................................................................................. +2.5V Maximum VDD33, VDDA33 ................................................................................................................. +4.6V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 7.1 When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. When internal power FET operation of these pins is enabled, these pins may be simultaneously shorted to ground or any voltage up to 3.63V indefinitely, without damage to the device as long as VDD33 and VDDA33 are less than 3.63V and TA is less than 70C.
Note 7.2
7.2
DC Electrical Characteristics
(TA = 0C - 70C, VDD33, VDDA33 = +3.3 V 0.3 V, VDD18, VDD18PLL = +1.8 V 10%,) PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
I,IPU & IPD Type Input Buffer Low Input Level High Input Level Pull Down Pull Up VILI VIHI PD PU 2.0 72 58 0.8 V V A A TTL Levels
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
PARAMETER IS Type Input Buffer Low Input Level High Input Level Hysteresis ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O8. O8PU & 08PD Type Buffer Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VILI VIHI VHYSI 2.0 500
0.8
V V mV
TTL Levels
VILCK VIHCK 2.2
0.4
V V
IIL IIH
-10 -10
+10 +10
A mA
VIN = 0 VIN = VDD33
VOL
0.4
V
IOL = 8 mA @ VDD33= 3.3V IOH = -8mA @ VDD33= 3.3V VIN = 0 to VDD33 (Note 7.3)
High Output Level
VOH
VDD33 - 0.4
V
Output Leakage
IOL PD
-10
+10
A A A
Pull Down
72
Pull Up I/O8, I/O8PU & I/O8PD Type Buffer Low Output Level
PU
58
VOL
0.4
V
IOL = 8 mA @ VDD33= 3.3V IOH = -8 mA @ VDD33= 3.3V VIN = 0 to VDD33 (Note 7.3)
High Output Level
VOH
VDD33 - 0.4 -10 +10
V
Output Leakage
IOL PD
A
Pull Down
72
A
Pull Up
PU
58
A
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
PARAMETER IO-U (Note 7.4) Integrated Power FET for GPIO8 & GPIO10 Output Current
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
IOUT ISC RDSON tDSON
100
mA
GPIO8 or 10; VdropFET = 0.23V GPIO8 or 10; VoutFET = 0V GPIO8 or 10; IFET = 70mA GPIO8 or 10; CLOAD = 10F
Short Circuit Current Limit
140
mA s
On Resistance
2.1
Output Voltage Rise Time Integrated Power FET for GPIO11) Output Current
800
IOUT ISC RDSON tDSON ICCINIT
200
mA
GPIO11; VdropFET = 0.46V GPIO11; VoutFET = 0V GPIO11; IFET = 70mA GPIO11; CLOAD = 10F @ VDD18, VDD18PLL = 1.8V @ VDD33, VDDA33 = 3.3V @ VDD18, VDD18PLL = 1.8V @ VDD33, VDDA33 = 3.3V @ VDD18, VDD18PLL = 1.8V @ VDD33, VDDA33 = 3.3V @ VDD18, VDD18PLL = 1.8V @ VDD33, VDDA33 = 3.3V
Short Circuit Current Limit
181
mA s mA mA mA mA mA mA A A
On Resistance
2.1
Output Voltage Rise Time Supply Current Unconfigured
800 45 10 60 20 60 30 70 30 180 240
Supply Current Active (Full Speed)
ICC
35 15
Supply Current Active (High Speed)
ICC
45 15
Supply Current Standby
ICSBY
160 215
Note 7.3 Note 7.4 Note 7.5
Output leakage is measured with the current pins in high impedance. See Appendix A for USB DC electrical characteristics. The Maximum power dissipation parameters of the package should not be exceeded
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DATASHEET
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Note 7.6
The assignment of each Integrated Card Power FET to a designated Card Connector is controlled by both firmware and the specific board implementation. Firmware will default to the settings listed in Table 9.1, "GPIO Usage," on page 26
7.3
Capacitance
TA = 25C; fc = 1MHz; VDD18, VDD18PLL = 1.8V LIMITS PARAMETER SYMBOL CIN MIN TYP MAX 20 UNIT pF TEST CONDITION All pins except USB pins (and pins under test tied to AC ground)
Clock Input Capacitance
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
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5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Chapter 8 Packaging
Figure 8.1 USB2231/USB2232 128-Pin TQFP Package Outline Table 8.1 USB2231/USB2232 128-Pin TQFP Package Parameters
MIN A A1 A2 D D1 E E1 H L L1 e q W R1 R2 ccc 0o 0.13 0.08 0.08 ~ Notes:
1. Controlling Unit: millimeter. 2. Tolerance on the true position of the leads is 0.035 mm maximum. Package body dimensions D1 and E1 do not include the mold protrusion. 3. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC USB2231/USB2232 25 Revision 1.3 (07-12-05)
NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.40 Basic ~ 0.18 ~ ~ ~
MAX 1.20 0.15 1.05 16.20 14.20 16.20 14.20 0.20 0.75 ~ 7o 0.23 ~ 0.20 0.08
REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
~ 0.05 0.95 15.80 13.80 15.80 13.80 0.09 0.45 ~
DATASHEET
5th Generation Hi-Speed USB Flash Media and CIR Controller with Integrated Card Power FETs
Datasheet
Chapter 9 GPIO Usage
Table 9.1 GPIO Usage
NAME GPIO1 GPIO2 GPIO3 GPIO4 ACTIVE LEVEL H H H H SYMBOL Flash Media Activity LED EE_CS V_BUS EE_DIN/ EE_DOUT/ xDID HS_IND/ SD_CD A16/ROMEN EE_CLK/ UNCONF_LED MS_PWR_CTRL/ CRD_PWR0 CF_PWR_CTRL SM_PWR_CTRL/ CRD_PWR1 SD/MMC_PWR_CTRL/ CRD_PWR2 MS_ACT_IND/ Media Activity/ CIR_SD DESCRIPTION AND NOTE Indicates media activity. Media or USB cable must not be removed with LED lit. Serial EE PROM chip select USB V bus detect Serial EE PROM input/output and xD Identify HS Indicator LED or SD Card Detect Switch input A16 address line connect for DFU or debug LED indicator optional. Serial EE PROM clock output or Unconfigured LED. Memory Stick Card Power Control, or Internal Power FET0. CompactFlash Card Power Control SmartMedia Card Power Control, or Internal Power FET1. SD/MMC Card Power Control, or Internal Power FET2. Memory Stick Activity Indicator, or Media Activity LED or CIR Receiver Shutdown.
GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12
H H H L L L L H
Note 9.1
Function assignment may change with ROM code revision or external firmware use. ROM Code -00 cannot be used, external firmware must be used to obtain proper functionality. Subsequent ROM codes will contain proper functionality.Consult firmware release notes for exact functionality for that release.
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SMSC USB2231/USB2232

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